Phase-locked loop (PLL) circuits are widely used in integrated circuit design, such as in the design of receivers. PLL circuits are basically closed-loop frequency control systems whose functioning is based on the phase sensitive detection of the phase difference between an input signal and an output signal.
FIG. 1 illustrates a conventional PLL circuit, which includes phase frequency detector (PFD) 20, pump 22, loop filter 24, voltage-controlled oscillator (VCO) 26, feedback (FB) divider 28, and start-up circuit 32. Input signal S_in is input into the PLL circuit and an output signal S_out is generated by the PLL.
A schematic diagram of start-up circuit 32 is shown in FIG. 2. Start-up circuit 32 includes cycle-counter 34, which counts the cycles of the input signal S_in and controls a voltage Vcoin to be applied to node 36 in FIG. 1. Starting from the first cycle of the input signal, switches 38 in FIG. 2 are closed and a voltage is applied to diodes 40 so that the divided voltage Vcoin is output to node 36 in FIG. 1. Accordingly, loop filter 24, which includes capacitors, is charged and the voltage Vcoin at node 36 increases due to the charging of the capacitors. The frequency F_vco of the signal S_vco outputted by VCO 26 thus increases.
Cycle-counter 34 and the entire start-up circuit 32 are turned off after a certain number, for example, 64 cycles of the input signal S_in. At which time, the frequency F_vco of signal S_vco is at an initial frequency. It is realized that the initial frequency is affected by several factors. For example, for a 50 MHz input signal, start-up circuit 32 is turned on for 1.28 microseconds. However, when the input signal has a frequency of 10 MHz, start-up circuit 32 is turned on for 6.4 microseconds. Such a significant difference in the frequencies of the input signals causes the different lock time of PLL circuits. For example, lock time may be 1.28 microseconds or 6.4 microseconds.
Further, at the time start-up circuit 32 is turned off, the initial frequency may have already exceeded the minimum operated frequency specified by the specification. Such a high frequency thus cannot be sent out of the PLL circuit before it is decreased. Referring again to FIG. 1, gating circuit 30 is added to gate the initial frequency. Gating circuit 30 blocks the signal generated by VCO 26 from being sent out of the PLL circuit until the frequency is reduced to a target frequency. To achieve such a function, gating circuit 30 needs to compare the signal generated by VCO 26 with a reference signal having the target frequency. However, due to the phase difference between the signal generated by VCO 26 and the reference signal, gating circuit 30 may output glitches that have much narrower pulses than required.
An additional problem of the conventional PLL circuit is caused by process, voltage, and temperature (PVT) variations, which cause different PLL circuits, although having a same design, to work on different process corners, such as fast-fast (FF) corner, slow-slow (SS) corner, and the like. Even for a same input signal, the initial frequencies of circuits working at the FF corner may have exceeded the minimum operated frequency, while the initial frequencies of the circuits working at the SS corner still have frequencies well below the minimum operated frequency. To ensure that the minimum operated frequency is not exceeded, the design of the PLL circuits may be adjusted so that the initial frequencies of the circuits working at the FF corner are also below the minimum operated frequency. Unfortunately, this may cause the circuits working at the SS corner to fail to start oscillating. Therefore, the conventional PLL circuits have subtle problems difficult to overcome. New PLL circuits and new start-up circuits are thus needed.